Time： 2024-08-18 韋克威科技

Reliability and Failure Analysis of Electronic Components (III)

Microelectronics Packaging Technology and Failure

1. Classification of microelectronic packaging:

? Zero level packaging:Connect the chip solder pads with the solder pads of each level of packaging through interconnect technology;

? First level packaging (device level packaging):Package one or more IC chips with suitable materials and connect the solder pads of the chips to the outer pins of the package using wire bonding (WB), tape automated bonding (TAB), and flip chip bonding (FC) to make them functional devices or components, including single-chip module SCM and multi chip module MCM

? Secondary packaging (PCB packaging):Install first level microelectronic packaging products and passive components together onto printed boards or other substrates to become components or complete machines.

? Third level packaging (system level packaging):Connect bipolar packaged products to the motherboard through layer selection, interconnect sockets, or flexible circuit boards to form a three-dimensional package, forming a complete machine system (three-dimensional assembly technology)

2. The Failure Mechanism of Microelectronics

Vicorv High-Reliability Electronic Components

(1) Thermal/mechanical failure

Brittle fracture

When the stress exceeds a certain value, brittle materials such as ceramics, glass, and silicon are prone to brittle fracture. Fracture usually occurs in areas with initial cracks and scratches. When the original cracks propagate to the active area of the device, the device will fail.

Stress Migration

Introduction:Copper interconnects replace aluminum interconnects. Although copper has lower electrical resistivity and stronger resistance to electromigration and stress migration, stress migration induces voids, leading to increased resistance or even complete fracture

Condition for occurrence:Stress gradient - caused by thermal mismatch between insulating medium and copper

Location:Stress concentration areas such as through holes and metal wire edges

Influencing factors:Stress, stress gradient, interconnect structure, operating temperature, adhesion of metal dielectric interface, microstructure of interconnect materials

Stress migration voids on copper wires

(2) Electrical failure

Electronic Migration

When a strong current passes through a metal wire, metal ions and other factors will move under the interaction of the current and other factors, forming pores or cracks inside the wire

reason:The diffusion of metal ions under the action of an electric field is caused by different mechanisms in different materials:

Welding point:Lattice diffusion

Aluminum interconnect:Grain boundary diffusion

Copper interconnect:Surface diffusion

drive:The comprehensive force generated by the exchange of momentum between electrons and ions and the external electric field, the diffusion force generated by non-equilibrium ion concentration, mechanical stress, and thermal stress

Influencing factors:

Geometric factors:Length, line width, corner, step, contact hole, etc

Material properties:Copper is the best, aluminum is inferior, and aluminum copper alloy is in between

(3) Metal migration

? Failure mode: Increased resistance or open circuit of metal interconnects

? Failure mechanism: electronic wind effect

? Production conditions: Current density greater than 10E5A/cm2

high temperature

Corrective measures: high-temperature deposition, increasing aluminum particle diameter, doping with copper, reducing working temperature, reducing steps, copper interconnection, planarization process

Electromigration of interconnects and solder joints

(4) Latch up effect - parasitic PNPN effect

Due to the parasitic transistor effect of MOS transistors (multiple transistors are formed under CMOS transistors, which may form a circuit on their own), if the circuit accidentally encounters conditions that turn on the parasitic transistor, the parasitic circuit will greatly affect the operation of the normal circuit, causing the original MOS circuit to withstand a large current greater than the normal state, which can quickly burn out the circuit.

In the locked state, the device forms a short circuit between the power supply and ground, causing high current, overvoltage stress, and device damage

Latch failure of communication interface integrated circuit

(5) Hot Carrier Injection Effect

When the gate voltage Vg is lower than the drain voltage Vd, the channel under the gate insulating film is pinched off, and the electric field near the drain increases;

Electrons flowing through this region at the source become hot electrons, and collisions increase - avalanche hot carriers at the drain;

Inject into the gate silicon dioxide film to generate traps and interface energy levels, increase the threshold voltage, increase or fluctuate the oxide layer charge, and degrade the device performance

(6) Time dependent dielectric breakdown

Breakdown model: I/E (hole breakdown), E (thermochemical breakdown)

I/E model: Electron penetration through oxide film ? Generate electron traps and hole traps+electron hole pairs ? Holes tunnel back into the oxide layer, forming a current ? Holes are easily captured by traps ? Generate an electric field in the oxide layer ? The local current at the defect continuously increases, forming positive feedback ? When traps overlap and form a conductive channel, the oxide layer is broken down.

Model E: Thermodynamic process, where dipole interactions under thermal stress and external electric field break down Si-O bonds and result in breakdown.

3. Electrochemical failure

Metal migration - The growth of metal dendrites starting from the bonding pad is an electrolytic process in which metal ions migrate from the anode region to the cathode region.

Phenomenon: The leakage current in the bridge connection area increases, and even short circuits occur

Migration ions: Ag, Pb, Sn, Au, Cu

Methods to prevent silver migration:

Use silver alloy;

When designing wiring layout, avoid excessive current and potential differences between adjacent conductors with fine spacing;

Set up a surface protective layer;

Clean the residue of soldering flux

? Corrosion

Condition: There is moisture and ion contamination inside the package

Essence: Electrochemical Reaction

Electrochemical Corrosion of Hybrid Integrated Circuits

Intermetallic compounds

? Advantages: Improved adhesion

? Disadvantages: Excessive intermetallic compounds can cause local embrittlement

tag: 軍用電子元器件微電子封裝

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Reliability and Failure Analysis of Electronic Components (III)